EECS 31/CSE 31/ICS 151 Homework 5 Questions with Solutions. View Questions Only View Questions with Strategies. Problem 1 Question (SR latch) Draw the output and timing diagram of a (a) NOR and (b) NAND implementation of an SR latch for the input signals depicted in Figure P6.2.

Nov 29, 2008 · Interrupt modules come in two flavors: level-triggered or edge-triggered. Because there are different usages of those terms, let me define them. Level-Triggered: A level-triggered interrupt module always generates an interrupt whenever the …